1. Field of the Invention
The present invention relates to a data signal output circuit which is used in a data signal output portion of a semiconductor memory device, etc., and a semiconductor memory device including a such data signal output circuit. Particularly, the present invention relates to an improvement in the output speed of the data signal output circuit when the supply voltage is low.
2. Description of the Related Art
In a semiconductor memory device, a sense amplifier reads out data stored in each memory cell, and the sense amplifier outputs the read data to extened circuits via a data signal output circuit. In order to increase the operation speed, there is proposed a semiconductor memory device in which operations are performed in synchronous with a clock signal. This type semiconductor memory device is further divided into two types. One is a synchronous type device in which the clock signal is input from outside, and the other is an asynchronous type device in which the clock signal is generated in the device. Alternatively, in this type semiconductor memory device, the data signal output circuit is also required to output a data signal in synchronous with the clock signal or with an output control signal which is synchronous with the clock signal.
In conventional data signal output circuits, a p-channel MOS transistor and an n-channel MOS transistor are serially connected between a high potential side and a low potential side of a power supply. The combination of these two transistors constitutes an inverter. An inverted data signal is applied to the gates of the p-channel MOB transistor and the n-channel MOS transistor. In order to output the data signal in synchronous with the output control signal, signals obtained by combining the output control signal with the data signal are applied to the gates of the transistors.
In the data signal output circuit, the output speed is required to be fast. Namely, the change times at the rising and the failing edges of the output data signal are desired to be as short as possible. The change times at the rising and the falling edges of the output data signal are determined by the drive abilities of the p-channel MOB transistor and the n-channel MOB transistor at the last stage, and the drive abilities of the transistors are determined by the sizes of the transistors. Therefore, the output speed are determined by the sizes of the transistors. However, when the sizes of the transistors are excessively large to reduce the times, the voltages of the power supply lines near these transistors fluctuate due to changes in the output signals of the inverter consisting of these transistors. When these voltage fluctuations are generated, it may happen that the output data signal of the sense amplifier temporarily changes and then returns to the correct state. When this phenomenon happens, it causes the data signal output speed to become slow. Therefore, because the sizes of the transistors of the last stage cannot be made to be very large, the data signal output signal cannot be very fast.
In order to improve the data signal output speed, a data signal output circuit having a latch circuit is proposed. The latch circuit is added at a stage preceeding the output circuit and the output data signal is stably held by the latch circuit when the output data signal is output from the output circuit. In this circuit, the sizes of the transistors can be made to be very large because the data signal is stably held by the latch circuit. Therefore, in this circuit, the output speed can be made to be very fast.
The latch signal which controls the latch circuit is generated from the clock signal, and the latch signal and the output control signal are complementary to each other. The duty ratios of these signals change when the supply voltage is low. Because these signals are complementary to each other, the duty ratios of the latch signal and the output control signal respectively change in different directions. For example, the conventional data signal output circuit starts to output the data signal when the latch signal changes to low and the output control signal changes to high. When the voltage of the power supply is normal, the data signal is output a certain time after the input data signal to the latch circuit changes. However, when the voltage of the power supply falls, the time during the latch signal is high and the output control signal is low also becomes longer. Therefore, the time from the change of the input data signal to the latch circuit until the data signal is output becomes longer. In this way, there occurs a problem that the data output speed decreases. Of course, when the voltage of the power supply is low, the data output speed of the sense amplifier also decreases, but the output data signal from the sense amplifier is further delayed because the duty ratios of latch signal and the output control signal change.
The latch circuit is added to the output circuit in order to increase the output speed. However, when the voltage of the power supply is low, the data signal output circuit having the latch circuit decreases the output speed. Namely, when the voltage of the power supply is low, the output speed of the output circuit having the latch circuit becomes slower than that of a circuit having no latch circuit.